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XC3S1500L, XC3S4000L,


XC3S1500L-4FG320C, XC3S1500L-4FGG320C, XC3S1500L-4FG456C, XC3S1500L-4FGG456C, XC3S1500L-4FG676C, XC3S1500L-4FGG676C,

Xilinx XC3S1500L

Product Overview
Manufacturer Xilinx
Category FPGA


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Spartan®-3L Field-Programmable Gate Arrays (FPGAs) consume less static current than corresponding members of the standard Spartan-3 family. Spartan-3L devices provide the identical function, features, timing, and pinout of the original Spartan-3 family. Features include programmable I/Os, Configurable Logic Blocks (CLBs), RAM blocks, Digital Clock Managers (DCMs), and Multiplier blocks.

Another power-saving benefit of the Spartan-3L family beyond static current reduction is the Hibernate mode, which lowers device power consumption to the lowest possible levels. For new designs, consider the Spartan-3A family, which offers both Hibernate and Suspend power-saving modes.

The three-member Spartan-3L family ranges in density from one to four million system gates and offers as many as 633 I/Os. All devices are specified to meet the –4 speed grade over the commercial temperature range.

This data sheet explains how the Spartan-3L family is different from the Spartan-3 family. For specifications and other technical information not contained in this document, refer to the Spartan-3 data sheet (DS099).


  • Power current reduction compared to Spartan-3 family:
    • Up to 60% less quiescent current
    • Up to 99% less quiescent current in Hibernate mode
  • Low cost, low power logic solution for high-volume, consumer-oriented applications
    • Densities as high as 62,000 logic cells
  • SelectIO™ signaling
    • Up to 633 I/O pins
    • Eighteen single-ended signal standards
    • Eight differential signal standards including LVDS and RSDS
    • Double Data Rate (DDR) support
  • Logic resources
    • Abundant logic cells with shift register capability
    • Wide multiplexers
    • Fast look-ahead carry logic
    • Dedicated 18 x 18 multipliers
    • JTAG logic compatible with IEEE 1149.1/1532
  • SelectRAM™ hierarchical memory
    • Up to 1,728 Kbits of total block RAM
    • Up to 432 Kbits of total distributed RAM
  • Digital Clock Manager (four DCMs)
    • Clock skew elimination
    • Frequency synthesis
    • High-resolution phase shifting
  • Eight global clock lines and abundant routing
  • Pin-compatible with Spartan-3 FPGAs
  • Pb-free packaging options
  • Fully supported by Xilinx ISE® development system
    • Synthesis, mapping, placement, and routing
  • MicroBlaze™ processor and other cores
  • Power estimation using XPower tools