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XQR2V1000, XQR2V3000, XQR2V6000,


XQR2V1000-4FG456M, XQR2V1000-4FG456V, XQR2V1000-4FG456H, XQR2V1000-4FG456N, XQR2V1000-4FG456R, XQR2V1000-4BG575M, XQR2V1000-4BG575V, XQR2V1000-4BG575H, XQR2V1000-4BG575N, XQR2V1000-4BG575R,

Xilinx XQR2V1000

Product Overview
Manufacturer Xilinx
Category FPGA


Request Support for for Xilinx XQR2V1000


The QPro Virtex®-II radiation-hardened family includes platform FPGAs developed for high performance, high-density, aerospace designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces.

The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 6 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays and other one-time-programmable devices. As shown in Table 1, the QPro Virtex-II radiation hardened family comprises three members, ranging from 1M to 6M system gates.

Table 1: Virtex-II Field-Programmable Gate Array Family Members

DeviceSystem GatesCLB (1 CLB = 4 slices = Max 128 bits)Multiplier BlocksSelectRAM BlocksDCMsMax I/O Pads(1)
Array Row x Col.SlicesMaximum Distributed RAM Kbits18 Kbit BlocksMax RAM (Kbits)
XQR2V10001M40 x 325,12016040407208432
XQR2V30003M64 x 5614,33644896961,72812720
XQR2V60006M96 x 8833,7921,0561441442,592121,104


Industry First Radiation-Hardened FPGA Solution

  • Guaranteed total ionizing dose to 200K Rad(Si)
  • Latch-up immune to LET > 160 MeV-cm2/mg
  • SEU in GEO upsets < 1.5E-6 per device day achievable with recommended redundancy implementation
  • Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)
  • Guaranteed over the full military temperature range (–55°C to +125°C)
  • 0.15 µm 8-Layer Metal Process with 0.12 µm High-Speed Transistors
  • Ceramic and Plastic Wire-Bond and Flip-Chip Grid Array Packages
  • IP-Immersion Architecture
    • Densities from 1M to 6M system gates
    • 300+ MHz internal clock speed (Advance Data)
    • 622+ Mb/s I/O (Advance Data)
  • SelectRAM™ Memory Hierarchy
    • 2.5 Mb of dual-port RAM in 18 Kbit block SelectRAM resources
    • Up to 1 Mb of distributed SelectRAM resources
  • High-Performance Interfaces to External Memory
    • DRAM interfaces
      • Network FCRAM
      • Reduced Latency DRAM
    • SRAM interfaces
      • SDR/DDR SRAM
      • QDR SRAM
    • CAM interfaces
  • Arithmetic Functions
    • Dedicated 18-bit x 18-bit multiplier blocks
    • Fast look-ahead carry logic chains
  • Flexible Logic Resources
    • Up to 67,584 internal registers/latches with Clock Enable
    • Up to 67,584 look-up tables (LUTs) or cascadable 16-bit shift registers
    • Wide multiplexers and wide-input function support
    • Horizontal cascade chain and sum-of-products support
    • Internal 3-state busing
  • High-Performance Clock Management Circuitry
    • Up to 12 DCM (Digital Clock Manager) modules
      • Precise clock de-skew
      • Flexible frequency synthesis
      • High-resolution phase shifting
    • 16 global clock multiplexer buffers
  • Active Interconnect Technology
    • Fourth generation segmented routing structure
    • Predictable, fast routing delay, independent of fanout
  • SelectIO™-Ultra Technology
    • Up to 824 user I/Os
    • 19 single-ended and six differential standards
    • Programmable sink current (2 mA to 24 mA) per I/O
    • Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
    • Differential Signaling
      • 622 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers
      • Bus LVDS I/O
      • Lightning Data Transport (LDT) I/O with current driver buffers
      • Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O
      • Built-in DDR input and output registers
    • Proprietary high-performance SelectLink Technology
      • High-bandwidth data path
      • Double Data Rate (DDR) link
      • Web-based HDL generation methodology
  • Supported by Xilinx Foundation Series™ and Alliance Series™ Development Systems
    • Integrated VHDL and Verilog design flows
    • Compilation of 10M system gates designs
    • Internet Team Design (ITD) tool
  • SRAM-Based In-System Configuration
    • Fast SelectMAP configuration
    • IEEE 1532 support
    • Partial reconfiguration
    • Unlimited reprogrammability
    • Readback capability
  • 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies
  • IEEE 1149.1 Compatible Boundary-Scan Logic Support