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Xilinx introduces the high-density QPro™ XQ17V16 series QML configuration PROM which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. The XQ17V16 is a 3.3V device with a storage capacity of 16 Mb and can operate in either a serial or byte wide mode. See Figure 1 for a simplified block diagram of the XQ17V16 device architecture.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
When the FPGA is in Master SelectMAP mode, it generates a configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. When the FPGA is in Slave SelectMAP mode, the PROM and the FPGA must both be clocked by an incoming signal. A free-running oscillator may be used to drive CCLK. See Figure 2.
Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.