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XA9536XL, XA9572XL, XA95144XL,


XA9536XL-15VQG44I, XA9536XL-15VQG44Q, XA9536XL-15VQG64I, XA9536XL-15VQG64Q, XA9536XL-15TQG100I, XA9536XL-15TQG100Q, XA9536XL-15CSG144I, XA9536XL-15CSG144Q, XA9572XL-15VQG44I, XA9572XL-15VQG44Q, XA9572XL-15VQG64I, XA9572XL-15VQG64Q, XA9572XL-15TQG100I, XA9572XL-15TQG100Q, XA9572XL-15CSG144I, XA9572XL-15CSG144Q, XA95144XL-15VQG44I, XA95144XL-15VQG44Q, XA95144XL-15VQG64I, XA95144XL-15VQG64Q, XA95144XL-15TQG100I, XA95144XL-15TQG100Q, XA95144XL-15CSG144I, XA95144XL-15CSG144Q,

Xilinx XA9536XL

Product Overview
Manufacturer Xilinx
Category CPLD


Request Support for for Xilinx XA9536XL


The XA9500XL 3.3V CPLD Automotive XA product family is targeted for leading-edge, high-performance automotive applications that require either automotive industrial (–40°C to +85°C ambient) or extended (–40°C to +105°C ambient) temperature reconfigurable devices.


  • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade.
  • Guaranteed to meet full electrical specifications over TA = -40° C to +105° C with TJ Maximum = +125° C (Q-grade)
  • System frequency up to 64.5 MHz (15.5 ns)
  • Available in small footprint packages
  • Optimized for high-performance 3.3V systems
    • 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals — ideal for multi-voltage system interfacing and level shifting
    • Technology: 0.35 μm CMOS process
  • Advanced system features
    • In-system programmable enabling higher system reliability through reduced handling and reducing production programming times
    • Superior pin-locking and routability with FastCONNECT™ II switch matrix allowing for multiple design iterations without board re-spins
    • Input hysteresis on all user and boundary-scan pin inputs to reduce noise on input signals
    • Bus-hold circuitry on all user pin inputs which reduces cost associated with pull-up resistors and reduces bus loading
    • Full IEEE Standard 1149.1 boundary-scan (JTAG) for in-system device testing
      • Fast concurrent programming
  • Slew rate control on individual outputs for reducing EMI generation
  • Refer to XC9500XL Family data sheet (DS054) for architecture description
  • Refer to XA9536XL data sheet (DS598), the XA9572XL data sheet (DS599), and the XA95144XL data sheet (DS600) for pin tables
  • Xilinx received ISO/TS 16949 Certification in March 2005.