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RELATED DEVICE CODES:

XC2C256, XC2C384, XC2C128, XC2C32A, XC2C64A,

RELATED MODEL NUMBERS:

XC2C128-6VQ100C, XC2C128-6VQ100I, XC2C128-6CP132C, XC2C128-6CP132I, XC2C128-6TQ144C, XC2C128-6TQ144I, XC2C128-6VQG100C, XC2C128-6VQG100I, XC2C128-6CPG132C, XC2C128-6CPG132I, XC2C128-6TQG144C, XC2C128-6TQG144I, XC2C128-7VQ100C, XC2C128-7VQ100I, XC2C128-7CP132C, XC2C128-7CP132I, XC2C128-7TQ144C, XC2C128-7TQ144I, XC2C128-7VQG100C, XC2C128-7VQG100I, XC2C128-7CPG132C, XC2C128-7CPG132I, XC2C128-7TQG144C, XC2C128-7TQG144I,

Xilinx XC2C256

Product Overview
Manufacturer Xilinx
Category CPLD

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Request Support for for Xilinx XC2C256

Description

The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved

This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.

A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.

Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature

DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.

By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.

Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.

Table 1: I/O Standards for XC2C128(1)

IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTT
LVTTL3.33.3N/AN/A
LVCMOS333.33.3N/AN/A
LVCMOS252.52.5N/AN/A
LVCMOS181.81.8N/AN/A
LVCMOS15(2)1.51.5N/AN/A
HSTL_11.51.50.750.75
SSTL2_12.52.51.251.25
SSTL3_13.33.31.51.5

Features:

  • Optimized for 1.8V systems
    • As fast as 5.7 ns pin-to-pin delays
    • As low as 13 μA quiescent current
  • Industry’s best 0.18 micron CMOS CPLD
    • Optimized architecture for effective logic synthesis
    • Multi-voltage I/O operation — 1.5V to 3.3V
  • Available in multiple package options
    • 100-pin VQFP with 80 user I/O
    • 144-pin TQFP with 100 user I/O
    • 132-ball CP (0.5mm) BGA with 100 user I/O
    • Pb-free available for all packages
  • Advanced system features
    • Fastest in system programming
      • 1.8V ISP using IEEE 1532 (JTAG) interface
    • IEEE1149.1 JTAG Boundary Scan Test
    • Optional Schmitt-trigger input (per pin)
    • Unsurpassed low power management
      • DataGATE enable (DGE) signal control
    • Two separate I/O banks
    • RealDigital 100% CMOS product term generation
    • Flexible clocking modes
      • Optional DualEDGE triggered registers
      • Clock divider (divide by 2,4,6,8,10,12,14,16)
      • CoolCLOCK
    • Global signal options with macrocell control
      • Multiple global clocks with phase selection per macrocell
      • Multiple global output enables
      • Global set/reset
    • Advanced design security
    • Open-drain output option for Wired-OR and LED drive
    • PLA architecture
      • Superior pinout retention
      • 100% product term routability across function block
    • Optional bus-hold, 3-state or weak pull-up on selected I/O pins
    • Optional configurable grounds on unused I/Os
    • Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
      • SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
    • Hot pluggable

Refer to the CoolRunner™-II family data sheet for architecture description.