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XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E,


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Xilinx XC2S50E

Product Overview
Manufacturer Xilinx
Category FPGA


Request Support for for Xilinx XC2S50E


The Spartan®-IIE Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The seven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz.

Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

The Spartan-IIE family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Table 1: Spartan-IIE FPGA Family Members

DeviceLogic CellsTypical System Gate Range (Logic and RAM)CLB Array (R x C)Total CLBsMaximum Available User I/O(1)Maximum Differential I/O PairsDistributed RAM BitsBlock RAM Bits
XC2S50E1,72823,000 - 50,00016 x 243841828324,57632K
XC2S100E2,70037,000 - 100,00020 x 306002028638,40040K
XC2S150E3,88852,000 - 150,00024 x 3686426511455,29648K
XC2S200E5,29271,000 - 200,00028 x 421,17628912075,26456K
XC2S300E6,91293,000 - 300,00032 x 481,53632912098,30464K
XC2S400E10,800145,000 - 400,00040 x 602,400410172153,600160K
XC2S600E15,552210,000 - 600,00048 x 723,456514205221,184288K



  • Second generation ASIC replacement technology
    • Densities as high as 15,552 logic cells with up to 600,000 system gates
    • Streamlined features based on Virtex®-E FPGA architecture
    • Unlimited in-system reprogrammability
    • Very low cost
    • Cost-effective 0.15 micron technology
  • System level features
    • SelectRAM™ hierarchical memory:
      • 16 bits/LUT distributed RAM
      • Configurable 4K-bit true dual-port block RAM
      • Fast interfaces to external RAM
    • Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant
    • Low-power segmented routing architecture
    • Dedicated carry logic for high-speed arithmetic
    • Efficient multiplier support
    • Cascade chain for wide-input functions
    • Abundant registers/latches with enable, set, reset
    • Four dedicated DLLs for advanced clock control
      • Eliminate clock distribution delay
      • Multiply, divide, or phase shift
    • Four primary low-skew global clock distribution nets
    • IEEE 1149.1 compatible boundary scan logic
  • Versatile I/O and packaging
    • Pb-free package options
    • Low-cost packages available in all densities
    • Family footprint compatibility in common packages
    • 19 high-performance interface standards
      • LVDS and LVPECL differential I/O
    • Up to 205 differential I/O pairs that can be input, output, or bidirectional
    • Hot swap I/O (CompactPCI friendly)
  • Core logic powered at 1.8V and I/Os powered at 1.5V, 2.5V, or 3.3V
  • Fully supported by powerful Xilinx® ISE® development system
    • Fully automatic mapping, placement, and routing
    • Integrated with design entry and verification tools
    • Extensive IP library including DSP functions and soft processors