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RELATED DEVICE CODES:

XC95216,

RELATED MODEL NUMBERS:

XC95216-10PQ160C, XC95216-10PQ160 I, XC95216-10PQG160C, XC95216-10PQG160 I, XC95216-10 HQ208C, XC95216-10 HQ208 I, XC95216-10 BG352 C, XC95216-10 BG352 I, XC95216-15PQ160C, XC95216-15PQ160 I, XC95216-15PQG160C, XC95216-15PQG160 I, XC95216-15 HQ208C, XC95216-15 HQ208 I, XC95216-15 BG352 C, XC95216-15 BG352 I, XC95216-20PQ160C, XC95216-20PQ160 I, XC95216-20PQG160C, XC95216-20PQG160 I, XC95216-20 HQ208C, XC95216-20 HQ208 I, XC95216-20 BG352 C, XC95216-20 BG352 I,

Xilinx XC95216

Product Overview
Manufacturer Xilinx
Category CPLD

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Description

The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview.

Features:

  • 10 ns pin-to-pin logic delays on all pins
  • fCNT to 111 MHz
  • 216 macrocells with 4,800 usable gates
  • Up to 166 user I/O pins
  • 5V in-system programmable
    • Endurance of 10,000 program/erase cycles
    • Program/erase over full commercial voltage and temperature range
  • Enhanced pin-locking architecture
  • Flexible 36V18 Function Block
    • 90 product terms drive any or all of 18 macrocells within Function Block
    • Global and product term clocks, output enables, set and reset signals
  • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
  • Programmable power reduction mode in each macrocell
  • Slew rate control on individual outputs
  • User programmable ground pin capability
  • Extended pattern security features for design protection
  • High-drive 24 mA outputs
  • 3.3V or 5V I/O capability
  • Advanced CMOS 5V FastFLASH™ technology
  • Supports parallel programming of more than one XC9500 concurrently
  • Available 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages (Note: 352-pin BGA packages are being discontinued for this device)