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RELATED DEVICE CODES:

XCS05, XCS10, XCS20, XCS30, XCS40, XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL,

RELATED MODEL NUMBERS:

XCS05-3PC84(1)C, XCS05-3PC84(1)I, XCS05-3VQ100(1)C, XCS05-3VQ100(1)I, XCS05-4PC84(1)C, XCS05-4PC84(1)I, XCS05-4VQ100(1)C, XCS05-4VQ100(1)I, XCS05-5PC84(1)C, XCS05-5PC84(1)I, XCS05-5VQ100(1)C, XCS05-5VQ100(1)I,

Xilinx XCS05

Product Overview
Manufacturer Xilinx
Category CPLD

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Description

The Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,XCS05 approach and in many cases are equivalent to mask programmed ASIC devices.

By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan and Spartan-XL families in the Spartan series have ten members, as shown in Table 1

Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays

DeviceLogic CellsMax System GatesTypical Gate Range (Logic and RAM)(1)CLB MatrixTotal CLBsNo. of Flip-flopsMax. Avail. User I/OTotal Distributed RAM Bits
XCS05 and XCS05XL2385,0002,000-5,00010 x 10100360773,200
XCS10 and XCS10XL46610,0003,000-10,00014 x 141966161126,272
XCS20 and XCS20XL95020,0007,000-20,00020 x 204001,12016012,800
XCS30 and XCS30XL136830,00010,000-30,00024 x 245761,53619218,432
XCS40 and XCS40XL186240,00013,000-40,00028 x 287842,016205(2)25,088

Features:

Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheets for more advanced members for the Spartan Series.

  • First ASIC replacement FPGA for high-volume production with on-chip RAM
  • Density up to 1862 logic cells or 40,000 system gates
  • Streamlined feature set based on XC4000 architecture
  • System performance beyond 80 MHz
  • Broad set of AllianceCORE and LogiCORE™ predefined solutions available
  • Unlimited reprogrammability
  • Low cost
  • System level features
    • Available in both 5V and 3.3V versions
    • On-chip SelectRAM™ memory
    • Fully PCI compliant
    • Full readback capability for program verification and internal node observability
    • Dedicated high-speed carry logic
    • Internal 3-state bus capability
    • Eight global low-skew clock or signal networks
    • IEEE 1149.1-compatible Boundary Scan logic
    • Low cost plastic packages available in all densities
    • Footprint compatibility in common packages
  • Fully supported by powerful Xilinx ISE® Classics development system
    • Fully automatic mapping, placement and routing

Additional Spartan-XL Family Features

  • 3.3V supply for low power with 5V tolerant I/Os
  • Power down input
  • Higher performance
  • Faster carry logic
  • More flexible high-speed clock network
  • Latch capability in Configurable Logic Blocks
  • Input fast capture latch
  • Optional MUX or 2-input function generator on outputs
  • 12 mA or 24 mA output drive
  • 5V and 3.3V PCI compliant
  • Enhanced Boundary Scan
  • Express Mode configuration