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RELATED DEVICE CODES:

XC95288XV, XC95288, XC95288XL,

RELATED MODEL NUMBERS:

XC95288XV-6 TQ144C, XC95288XV-6 TQ144I, XC95288XV-6PQ208C, XC95288XV-6PQ208I, XC95288XV-6FG256C, XC95288XV-6FG256I, XC95288XV-6CS280C, XC95288XV-6CS280I, XC95288XV-7 TQ144C, XC95288XV-7 TQ144I, XC95288XV-7PQ208C, XC95288XV-7PQ208I, XC95288XV-7FG256C, XC95288XV-7FG256I, XC95288XV-7CS280C, XC95288XV-7CS280I, XC95288XV-10 TQ144C, XC95288XV-10 TQ144I, XC95288XV-10PQ208C, XC95288XV-10PQ208I, XC95288XV-10FG256C, XC95288XV-10FG256I, XC95288XV-10CS280C, XC95288XV-10CS280I,

Xilinx XC95288XV

Product Overview
Manufacturer Xilinx
Category CPLD

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Request Support for for Xilinx XC95288XV

Description

Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC95288XV devices with equivalent XC95288XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support, and only one output bank is supported. See XCN07010 for details regarding this discontinuation, including device replacement recomendations for the XC95288XV CPLD.

Features:

  • 288 macrocells with 6,400 usable gates
  • Available in small footprint packages
    • 144-pin TQFP (117 user I/O pins)
    • 208-pin PQFP (168 user I/O pins)
    • 280-pin CSP (192 user I/O pins)
    • 256-pin FBGA (192 user I/O pins)
  • Optimized for high-performance 2.5V systems
    • Low power operation
    • Multi-voltage operation
  • Advanced system features
    • In-system programmable
    • Four separate output banks
    • Superior pin-locking and routability with Fast CONNECT™ II switch matrix
    • Extra wide 54-input Function Blocks
    • Up to 90 product-terms per macrocell with individual product-term allocation
    • Local clock inversion with three global and one product-term clocks
    • Individual output enable per output pin
    • Input hysteresis on all user and boundary-scan pin inputs
    • Bus-hold ciruitry on all user pin inputs
    • Full IEEE Standard 1149.1 boundary-scan (JTAG)
  • Fast concurrent programming
  • Slew rate control on individual outputs
  • Enhanced data security features
  • Excellent quality and reliability
    • 20 year data retention
    • ESD protection exceeding 2,000V