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RELATED DEVICE CODES:

XC2V40, XC2V80, XC2V250, XC2V500, XC2V1500, XC2V2000, XC2V3000, XC2V4000, XC2V6000, XC2V8000, XQ2V1000, XQ2V3000, XQ2V6000,

RELATED MODEL NUMBERS:

XC2V40-4CS144C, XC2V40-4CS144I, XC2V40-4CSG144C, XC2V40-4CSG144I, XC2V40-4FG256C, XC2V40-4FG256I, XC2V40-4FGG256C, XC2V40-4FGG256I, XC2V40-5CS144C, XC2V40-5CS144I, XC2V40-5CSG144C, XC2V40-5CSG144I, XC2V40-5FG256C, XC2V40-5FG256I, XC2V40-5FGG256C, XC2V40-5FGG256I, XC2V40-6CS144C, XC2V40-6CS144I, XC2V40-6CSG144C, XC2V40-6CSG144I, XC2V40-6FG256C, XC2V40-6FG256I, XC2V40-6FGG256C, XC2V40-6FGG256I, XC2V40CS144C, XC2V40CS144I, XC2V40CSG144C, XC2V40CSG144I, XC2V40FG256C, XC2V40FG256I, XC2V40FGG256C, XC2V40FGG256I,

Xilinx XC2V40

Product Overview
Manufacturer Xilinx
Category FPGA

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Description

The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces.

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, the Virtex-II family comprises 11 members, ranging from 40K to 8M system gates.

Table 1: Virtex-II Field-Programmable Gate Array Family Members

DeviceSystem Gates

CLB(1 CLB = 4 slices = Max 128 bits)

Multiplier BlocksSelectRAM BlocksDCMsMax I/O Pads(1)
Array Row x Col.SlicesMaximum Distributed RAM Kbits18 Kbit BlocksMax RAM (Kbits)
XC2V4040K8 x 825684472488
XC2V8080K16 x 851216881444120
XC2V250250K24 x 161,5364824244328200
XC2V500500K32 x 243,0729632325768264
XC2V10001M40 x 325,12016040407208432
XC2V15001.5M48 x 407,68024048488648528
XC2V20002M56 x 4810,75233656561,0088624
XC2V30003M64 x 5614,33644896961,72812720
XC2V40004M80 x 7223,0407201201202,16012912
XC2V60006M96 x 8833,7921,0561441442,592121,104
XC2V80008M112 x 10446,5921,4561681683,024121,108

Features:

  • Industry First Platform FPGA Solution
  • IP-Immersion Architecture
    • Densities from 40K to 8M system gates
    • 420 MHz internal clock speed (Advance Data)
    • 840+ Mb/s I/O (Advance Data)
  • SelectRAM™ Memory Hierarchy
    • 3 Mb of dual-port RAM in 18 Kbit block SelectRAM resources
    • Up to 1.5 Mb of distributed SelectRAM resources
  • High-Performance Interfaces to External Memory
    • DRAM interfaces
      • SDR / DDR SDRAM
      • Network FCRAM
      • Reduced Latency DRAM
    • SRAM interfaces
      • SDR / DDR SRAM
      • QDR™ SRAM
    • CAM interfaces
  • Arithmetic Functions
    • Dedicated 18-bit x 18-bit multiplier blocks
    • Fast look-ahead carry logic chains
  • Flexible Logic Resources
    • Up to 93,184 internal registers / latches with Clock Enable
    • Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers
    • Wide multiplexers and wide-input function support
    • Horizontal cascade chain and sum-of-products support
    • Internal 3-state bussing
  • High-Performance Clock Management Circuitry
    • Up to 12 DCM (Digital Clock Manager) modules
      • Precise clock de-skew
      • Flexible frequency synthesis
      • High-resolution phase shifting
    • 16 global clock multiplexer buffers
  • Active Interconnect Technology
    • Fourth generation segmented routing structure
    • Predictable, fast routing delay, independent of fanout
  • SelectIO™-Ultra Technology
    • Up to 1,108 user I/Os
    • 19 single-ended and six differential standards
    • Programmable sink current (2 mA to 24 mA) per I/O
    • Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
    • PCI-X compatible (133 MHz and 66 MHz) at 3.3V
    • PCI compliant (66 MHz and 33 MHz) at 3.3V
    • CardBus compliant (33 MHz) at 3.3V
    • Differential Signaling
      • 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers
      • Bus LVDS I/O
      • Lightning Data Transport (LDT) I/O with current driver buffers
      • Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O
      • Built-in DDR input and output registers
    • Proprietary high-performance SelectLink Technology
      • High-bandwidth data path
      • Double Data Rate (DDR) link
      • Web-based HDL generation methodology
  • Supported by Xilinx Foundation™ and Alliance Series™ Development Systems
    • Integrated VHDL and Verilog design flows
    • Compilation of 10M system gates designs
    • Internet Team Design (ITD) tool
  • SRAM-Based In-System Configuration
    • Fast SelectMAP configuration
    • Triple Data Encryption Standard (DES) security option (Bitstream Encryption)
    • IEEE 1532 support
    • Partial reconfiguration
    • Unlimited reprogrammability
    • Readback capability
  • 0.15 µm 8-Layer Metal Process with 0.12 µm High-Speed Transistors
  • 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies
  • IEEE 1149.1 Compatible Boundary-Scan Logic Support
  • Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Three Standard Fine Pitches (0.80 mm, 1.00 mm, and 1.27 mm)
  • Wire-Bond BGA Devices Available in Pb-Free Packaging (www.xilinx.com/pbfree)
  • 100% Factory Tested