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XQVR300, XQVR600, XQVR1000, XQV600E-6, XQV1000E-6, XQV2000E-6,


XQVR300-4CB228M, XQVR300-4CB228V, XQVR300-4CB228Q, XQVR300-4CG560M, XQVR300-4CG560V, XQVR300-4CG560Q, XQVR300-4M, XQVR300-4V, XQVR300-4Q, XQVR600-4CB228M, XQVR600-4CB228V, XQVR600-4CB228Q, XQVR600-4CG560M, XQVR600-4CG560V, XQVR600-4CG560Q, XQVR600-4M, XQVR600-4V, XQVR600-4Q, XQVR1000-4CB228M, XQVR1000-4CB228V, XQVR1000-4CB228Q, XQVR1000-4CG560M, XQVR1000-4CG560V, XQVR1000-4CG560Q, XQVR1000-4M, XQVR1000-4V, XQVR1000-4Q

Xilinx XQVR300

Product Overview
Manufacturer Xilinx
Category FPGA


Request Support for for Xilinx XQVR300


The QPro™ Virtex® family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 µm CMOS process. These advances make QPro Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex radiation-hardened family comprises the three members shown in Table 1.

Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the QPro Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.

Refer to the Virtex 2.5V FPGA commercial data sheet at http://www.xilinx.com/support/documentation/virtex.htm for more information on device architecture and timing specifications.

Table 1: QPro Virtex FPGA Radiation-Hardened FPGA Family Members

DeviceSystem GatesCLB ArrayLogic CellsMaximum Available I/OBlock RAM BitsMaximum Select RAM Bits


  • 0.22 µm 5-layer epitaxial process
  • QML certified
  • Radiation-hardened FPGAs for space and satellite applications
  • Guaranteed total ionizing dose to 100K Rad(si)
  • Latch-up immune to LET = 125 MeV cm2/mg
  • SEU immunity achievable with recommended redundancy implementation
  • Guaranteed over the full military temperature range (–55°C to +125°C)
  • Fast, high-density Field-Programmable Gate Arrays
    • Densities from 100k to 1M system gates
    • System performance up to 200 MHz
    • Hot-swappable for Compact PCI
  • Multi-standard SelectIO™ interfaces
    • 16 high-performance interface standards
    • Connects directly to ZBTRAM devices
  • Built-in clock-management circuitry
    • Four dedicated delay-locked loops (DLLs) for advanced clock control
    • Four primary low-skew global clock distribution nets, plus 24 secondary global nets
  • Hierarchical memory system
    • LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register
    • Configurable synchronous dual-ported 4k-bit RAMs
    • Fast interfaces to external high-performance RAMs
  • Flexible architecture that balances speed and density
    • Dedicated carry logic for high-speed arithmetic
    • Dedicated multiplier support
    • Cascade chain for wide-input functions
    • Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset
    • Internal 3-state bussing
    • IEEE 1149.1 boundary-scan logic
    • Die-temperature sensing device
  • Supported by FPGA Foundation™ and Alliance Development Systems
    • Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager
    • Wide selection of PC and workstation platforms
  • SRAM-based in-system configuration
    • Unlimited reprogrammability
    • Four programming modes
  • Available to Standard Microcircuit Drawings. Contact Defense Supply Center Columbus (DSCC) for more information at http://www.dscc.dla.mil
    • 5962-99572 for XQVR300
    • 5962-99573 for XQVR600
    • 5962-99574 for XQVR1000