(818) 718-4100 sales@stock-point.com

Search Our Site

RELATED DEVICE CODES:

XC1736E, XC1736E, XC1765E, XC17128E, XC1765E, XC1765EL, XC17128E, XC17128EL, XC17256EL, XC17256E, XC17512L, XC1701, XC1701L, XC1704L, XC1702L,

RELATED MODEL NUMBERS:

XC1736EPD8C, XC1736EPD8i, XC1736ESO8C, XC1736ESO8i, XC1736EVO8C, XC1736EVO8i, XC1736EPC20C, XC1736EPC20i, XC1736EPDG8C, XC1736EPDG8i, XC1736ESOG8C, XC1736ESOG8i, XC1736EVOG8C, XC1736EVOG8i, XC1736EPCG20C, XC1736EPCG20i,

Xilinx XC1736E

Product Overview
Manufacturer Xilinx
Category PROM

Actions





Request Support for for Xilinx XC1736E

Description

FPGA Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode.

Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK.

If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor.

Features:

  • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs
  • Simple interface to the FPGA; requires only one user I/O pin
  • Cascadable for storing longer or multiple bitstreams
  • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
  • XC17128E/EL, XC17256E/EL, XC1701, and XC1700L series support fast configuration
  • Low-power CMOS floating-gate process
  • XC1700E series are available in 5V and 3.3V versionsXC1700L series are available in 3.3V only
  • Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP
  • Programming support by leading programmer manufacturers
  • Design support using the Xilinx Alliance and Foundation™ software packages
  • Guaranteed 20 year life data retention
  • Lead-free (Pb-free) packaging available