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RELATED DEVICE CODES:

XCR3032XL,

RELATED MODEL NUMBERS:

"XCR3032XL-5VQ44C, XCR3032XL-5VQ44I, XCR3032XL-5VQG44C, XCR3032XL-5VQG44I, XCR3032XL-5CS48C, XCR3032XL-5CS48I, XCR3032XL-5CSG48C, XCR3032XL-5CSG48I, XCR3032XL-7VQ44C, XCR3032XL-7VQ44I, XCR3032XL-7VQG44C, XCR3032XL-7VQG44I, XCR3032XL-7CS48C, XCR3032XL-7CS48I, XCR3032XL-7CSG48C, XCR3032XL-7CSG48I, XCR3032XL-10VQ44C, XCR3032XL-10VQ44I, XCR3032XL-10VQG44C, XCR3032XL-10VQG44I, XCR3032XL-10CS48C, XCR3032XL-10CS48I, XCR3032XL-10CSG48C, XCR3032XL-10CSG48I, "

Xilinx XCR3032XL

Product Overview
Manufacturer Xilinx
Category CPLD

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Description

The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are as fast as 4.5 ns with a maximum system frequency of 213 MHz.

Features:

  • Low power 3.3V 32 macrocell CPLD
  • 4.5 ns pin-to-pin logic delays
  • System frequencies up to 213 MHz
  • 32 macrocells with 750 usable gates
  • Available in small footprint packages
    • 48-ball CS BGA (36 user I/O pins)
    • 44-pin VQFP (36 user I/Os)
  • Optimized for 3.3V systems
    • Ultra-low power operation
    • Typical Standby Current of 17 μA at 25°C
    • 5V tolerant I/O pins with 3.3V core supply
    • Advanced 0.35 micron five layer metal EEPROM process
    • Fast Zero Power (FZP) CMOS technology
    • 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
  • Advanced system features
    • In-system programming
    • Input registers
    • Predictable timing model
    • Up to 23 available clocks per function block
    • Excellent pin retention during design changes
    • Full IEEE Standard 1149.1 boundary-scan (JTAG)
    • Four global clocks
    • Eight product term control terms per function block
  • Fast ISP programming times
  • Port Enable pin for dual function of JTAG ISP pins
  • 2.7V to 3.6V supply voltage at industrial temperature range
  • Programmable slew rate control per macrocell
  • Security bit prevents unauthorized access
  • Refer to the CoolRunner XPLA3 family data sheet (DS012) for architecture description