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RELATED DEVICE CODES:

XCV50E, XCV100E, XCV200E, XCV300E, XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E,

RELATED MODEL NUMBERS:

"XCV50E-6CS144C, XCV50E-6CS144I, XCV50E-6PQ240C, XCV50E-6PQ240I, XCV50E-6FG256C, XCV50E-6FG256I, XCV50E-7CS144C, XCV50E-7CS144I, XCV50E-7PQ240C, XCV50E-7PQ240I, XCV50E-7FG256C, XCV50E-7FG256I, XCV50E-8CS144C, XCV50E-8CS144I, XCV50E-8PQ240C, XCV50E-8PQ240I, XCV50E-8FG256C, XCV50E-8FG256I, "

Xilinx XCV50E

Product Overview
Manufacturer Xilinx
Category FPGA

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Request Support for for Xilinx XCV50E

Description

The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1.

Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.

Table 1: Virtex-E Field-Programmable Gate Array Family Members

DeviceSystem GatesLogic GatesCLB ArrayLogic CellsDifferential I/O PairsUser I/OBlockRAM BitsDistributed RAM Bits
XCV50E71,69320,73616 x 241,7288317665,53624,576
XCV100E128,23632,40020 x 302,7008319681,92038,400
XCV200E306,39363,50428 x 425,292119284114,68875,264
XCV300E411,95582,94432 x 486,912137316131,07298,304
XCV400E569,952129,60040 x 6010,800183404163,840153,600
XCV600E985,882186,62448 x 7215,552247512294,912221,184
XCV1000E1,569,178331,77664 x 9627,648281660393,216393,216
XCV1600E2,188,742419,90472 x 10834,992344724589,824497,664
XCV2000E2,541,952518,40080 x 12043,200344804655,360614,400
XCV2600E3,263,755685,58492 x 13857,132344804753,664812,544
XCV3200E4,074,387876,096104 x 15673,008344804851,9681,038,336

 



Features:

  • Fast, High-Density 1.8 V FPGA Family
    • Densities from 58 k to 4 M system gates
    • 130 MHz internal performance (four LUT levels)
    • Designed for low-power operation
    • PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
  • Highly Flexible SelectI/O+™ Technology
    • Supports 20 high-performance interface standards
    • Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s
  • Differential Signalling Support
    • LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
    • Differential I/O signals can be input, output, or I/O
    • Compatible with standard differential devices
    • LVPECL and LVDS clock inputs for 300+ MHz clocks
  • Proprietary High-Performance SelectLink™ Technology
    • Double Data Rate (DDR) to Virtex-E link
    • Web-based HDL generation methodology
  • Sophisticated SelectRAM+™ Memory Hierarchy
    • 1 Mb of internal configurable distributed RAM
    • Up to 832 Kb of synchronous internal block RAM
    • True Dual-Port BlockRAM capability
    • Memory bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels)
    • Designed for high-performance Interfaces to External Memories
    • 200 MHz ZBT* SRAMs
    • 200 Mb/s DDR SDRAMs
    • Supported by free Synthesizable reference design
  • High-Performance Built-In Clock Management Circuitry
    • Eight fully digital Delay-Locked Loops (DLLs)
    • Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications
    • Clock Multiply and Divide
    • Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard
  • Flexible Architecture Balances Speed and Density
    • Dedicated carry logic for high-speed arithmetic
    • Dedicated multiplier support
    • Cascade chain for wide-input function
    • Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset
    • Internal 3-state bussing
    • IEEE 1149.1 boundary-scan logic
    • Die-temperature sensor diode
  • Supported by Xilinx Foundation™ and Alliance Series™ Development Systems
    • Further compile time reduction of 50%
    • Internet Team Design (ITD) tool ideal for million-plus gate density designs
    • Wide selection of PC and workstation platforms
  • SRAM-Based In-System Configuratio
    • Unlimited re-programmability
  • Advanced Packaging Options
    • 0.8 mm Chip-scale
    • 1.0 mm BGA
    • 1.27 mm BGA
    • HQ/PQ
  • 0.18 μm 6-Layer Metal Process
  • 100% Factory Tested