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Xilinx XCR3256XL

Product Overview
Manufacturer Xilinx
Category CPLD


Request Support for for Xilinx XCR3256XL


The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.

TotalCMOS Design Technique for Fast Zero Power

CoolRunner XPLA3 CPLDs offer a TotalCMOS? solution, both in process technology and design technique. These CPLDs employ a cascade of CMOS gates to implement their sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx CPLDs to offer devices that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3256XL TotalCMOS CPLD (data taken with 16 resetable up/down, 16-bit counters at 3.3V, 25?C).


  • Low power 3.3V 256 macrocell CPLD
  • 7.0 ns pin-to-pin logic delays
  • System frequencies up to 154 MHz
  • 256 macrocells with 6,000 usable gates
  • Available in small footprint packages
    • 144-pin TQFP (120 user I/O pins)
    • 208-pin PQFP (164 user I/O)
    • 256-ball FBGA (164 user I/O)
    • 280-ball CS BGA (164 user I/O)
  • Optimized for 3.3V systems
    • Ultra low power operation
    • Typical Standby Current of 18 μA at 25° C
    • 5V tolerant I/O pins with 3.3V core supply
    • Advanced 0.35 micron five layer metal EEPROM process
    • Fast Zero Power™ (FZP) CMOS design technology
    • 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O)
  • Advanced system features
    • In-system programming
    • Input registers
    • Predictable timing model
    • Up to 23 clocks available per function block
    • Excellent pin retention during design changes
    • Full IEEE Standard 1149.1 boundary-scan (JTAG)
    • Four global clocks
    • Eight product term control terms per function block
  • Fast ISP programming times
  • Port Enable pin for additional I/O
  • 2.7V to 3.6V supply voltage at industrial grade voltage range
  • Programmable slew rate control per output
  • Security bit prevents unauthorized access
  • Refer to the CoolRunner™ XPLA3 family data sheet (DS012) for architecture description